Matrix Orbital Corp

We're running an LK204-25 on the TWI port of AT91SAM7S256. The LCD module shares the bus with an EEPROM, 24LC64. Running from system power-up, everything is fine and we can do everything we need to do: display data, read pushbuttons.

When we reset the AT91 processor with its RESET pin we occasionally wind up with a hung system. Debugger shows that we're waiting for a TWI interchange to complete, a logic probe shows that the I2C clock line is being held low. This can persist over many resets, although merely waiting 30 or 60 seconds will not consistently break the impasse. Briefly killing power to the LK204-25 will break the impasse.

My suspicion is that the system hangs when the RESET comes in the middle of a pushbutton read on the LK204, and interrupts the normal I2C sequence. Is there any info about the LK204 operation that could prove or disprove this idea?

Mel.

Hi,

Thank you for posting on the forum.

I am not sure about the pull and stretch of the SCL low. I checked the data sheet and it says that the TWI hardware would pull and stretch SCL low when the software does not get to clear a TWI interrupt. This might be what is happening when your uC is reset. I have checked the code though and there should be a way out of the interrupt no matter what; but since I do not have your system to test with, mine is only a theory.

Maybe you can try taking off the other I2C slave devices on the bus, and see if you have the same problem with just the display on the bus?

Thanks,